As semiconductor trends continue toward decreased size and increased packaging density, every aspect of semiconductor fabrication processes is scrutinized in an attempt to maximize efficiency in semiconductor fabrication and throughput. Many factors contribute to fabrication of a semiconductor. For example, at least one photolithographic process can be used during fabrication of a semiconductor. This particular factor in the fabrication process is highly scrutinized by the semiconductor industry in order to improve packaging density and precision in semiconductor structure.
Lithography is a process in semiconductor fabrication that generally relates to transfer of patterns between media. More specifically, lithography refers to transfer of patterns onto a thin film that has been deposited onto a substrate. The transferred patterns then act as a blueprint for desired circuit components. Typically, various patterns are transferred to a photoresist (e.g., radiation-sensitive film), which overlies the thin film on the substrate during an imaging process described as “exposure” of the photoresist layer. During exposure, the photoresist is subjected to an illumination source (e.g. UV-light, electron beam, X-ray), which passes through a pattern template, or reticle, to print the desired pattern in the photoresist. Upon exposure to the illumination source, radiation-sensitive qualities of the photoresist permit a chemical transformation in exposed areas of the photoresist, which in turn alters the solubility of the photoresist in exposed areas relative to that of unexposed areas. When a particular solvent developer is applied, exposed areas of the photoresist are dissolved and removed, resulting in a three-dimensional pattern in the photoresist layer. This pattern is at least a portion of the semiconductor device that contributes to final function and structure of the device, or wafer.
Techniques, equipment and monitoring systems have concentrated on preventing and/or decreasing defect occurrence within lithography processes. For example, aspects of resist processes that are typically monitored can comprise: whether the correct mask has been used; whether resist film qualities are acceptable (e.g., whether resist is free from contamination, scratches, bubbles, striations, . . . ); whether image quality is adequate (e.g., good edge definition, line-width uniformity, and/or indications of bridging); whether critical dimensions are within specified tolerances; whether defect types and densities are recorded; and/or whether registration is within specified limits; etc. Such defect inspection task(s) have progressed into automated system(s) based on both automatic image processing and electrical signal processing.
Current methods of wafer fabrication can produce “footing,” or “T-topping,” as an undesirable side effect. Footing typically occurs during post-exposure delay (PED), which is the time between exposure and post-exposure bake (PEB). For example, ambient vapors having base compounds (e.g., amines, ammonia, etc.) can react with the photo-acids created during exposure. Once such ambient bases are absorbed into the surface of a resist, the acids are neutralized, resulting in a reduced solubility in the surface of the resist as compared to the rest of the resist. The less-soluble “skin” on the surface develops at a slower rate than the resist material between the surface and the substrate, resulting in the “T-top”, or “foot” formation.
As lithographic techniques are pushed to their limits, smaller and smaller critical dimensions (CDs) are desired to maximize chip performance. Thus, chip manufacture is governed largely by wafer CD, which is defined as the smallest allowable width of, or space between, lines of circuitry in a semiconductor device. As methods of wafer manufacture are improved, wafer CD is decreased, which in turn requires finer and finer line edges to be produced. Specifically, footing represents a significant problem in the sub-0.25 μm range. As critical dimensions proceed below the sub-0.25 μm threshold, footing becomes increasingly detrimental to the performance of a finished chip. There is an unmet need in the art for systems and methods that facilitate early detection of conditions that can lead to footing, and compensatory measures that can mitigate the potential for footing, thereby reducing production costs and increasing quality and throughput.